For the design of digital circuits (e.g., on the scale of Very Large Scale Integration (VLSI) technology), designers often employ computer-aided techniques. Standard languages such as Hardware Description Languages (HDLs) have been developed to describe digital circuits to aid in the design and simulation of complex digital circuits. Several hardware description languages, such as VHDL and Verilog, have evolved as industry standards. VHDL and Verilog are general-purpose hardware description languages that allow definition of a hardware model at the gate level, the register transfer level (RTL) or the behavioral level using abstract data types. As device technology continues to advance, various product design tools have been developed to adapt HDLs for use with newer devices and design styles.
In designing an integrated circuit with an HDL code, the code is first written and then compiled by an HDL compiler. The HDL source code describes at some level the circuit elements, and the compiler produces an RTL netlist from this compilation. The RTL netlist is typically a technology independent netlist in that it is independent of the technology/architecture of a specific vendor's integrated circuit, such as field programmable gate arrays (FPGA) or an application-specific integrated circuit (ASIC). The RTL netlist corresponds to a schematic representation of circuit elements (as opposed to a behavioral representation). A mapping operation is then performed to convert from the technology independent RTL netlist to a technology specific netlist, which can be used to create circuits in the vendor's technology/architecture. It is well known that FPGA vendors utilize different technology/architecture to implement logic circuits within their integrated circuits. Thus, the technology independent RTL netlist is mapped to create a netlist, which is specific to a particular vendor's technology/architecture.
One operation, which is often desirable in this process, is to plan the layout of a particular integrated circuit and to control timing problems and to manage interconnections between regions of an integrated circuit. This is sometimes referred to as “floor planning”. A typical floor planning operation divides the circuit area of an integrated circuit into regions, sometimes called “blocks,” and then assigns logic to reside in a block. These regions may be rectangular or non-rectangular. This operation has two effects: the estimation error for the location of the logic is reduced from the size of the integrated circuit to the size of the block (which tends to reduce errors in timing estimates), and the placement and routing typically runs faster because as it has been reduced from one very large problem into a series of simpler problems.
After placement of components on the chip and routing of wires between components, timing analysis (e.g., timing simulation, or static timing analysis) can be performed to accurately determine the signal delays between logic elements. Back annotation can be performed to update a more-abstract design with information from later design stages. For example, back annotation reads wire delay information and placement information from the placement and route database to annotate the logic synthesis design. Back annotated delay information can be used to identify critical paths where the timing requirements are not satisfied; and logic synthesis may be improved to meet the timing requirements.
A typical software program for logic synthesis uses a delay estimator function based on the fanout of a net. Since all logic elements corresponding to a net with a certain fanout are assumed to have the same wire delay, the estimated delay information is not very accurate. In reality the wire delay depends on the length of the wire routed from one logic element to the next logic element. There is a higher correlation between placement distance and wire delay than between fanout and wire delay. Due to the error in the delay estimator in logic synthesis, a solution appears to be valid during logic synthesis may be found invalid after the placement and routing operation.
After the design layout (e.g., the placement and routing), only limited optimizations like resizing or buffering (known as in place optimizations) are typically performed. However, in place optimizations can provide only limited improvements. When the in place optimization cannot adjust the solution to meet the timing constraint, adjustment to the logic synthesis may be performed, leading to the expensive iteration between logic synthesis and placement and routing.
Synthesis and optimizations of logic circuits for reducing the delay of critical paths is an important step in designing and implementing a logic circuit. It is desirable to have accurate wire delay information to obtain optimization results of good qualities, since inaccurate delay estimation in the synthesis stage may lead to invalid design layout. If logic synthesis has to be improved to meet the timing requirement (e.g., slack requirement), expensive iterations between synthesis and design layout have to be performed. Note that slack is the difference between the desired delay and the actual (estimated or computed) delay. When the desired delay is larger than the actual delay, the slack is positive; otherwise, the slack is negative. Typically, it is necessary to make the slack positive (or close to zero) to meet the timing requirement (e.g., through reducing the wire delay to increase the slack). For example, during synthesis, a total negative slack algorithm (e.g., used in a circuit design compiler, Synplify, available from Synplicity, Inc., California) considers all instances whose slack is negative as candidates for improvement, since any one of the candidates with negative slack could become critical after physical design. It is typical to make the slack positive to ensure that the timing requirements are met.